April 21, 2018

Silicon nanosheet-based builds 5nm transistor

19 June 2017, 02:10 | Rudolph Thomas

IBM Research scientist Nicolas Loubet holds a wafer of chips with 5nm silicon nanosheet transistors

IBM Research scientist Nicolas Loubet holds a wafer of chips with 5nm silicon nanosheet transistors

The building process is similar (ultraviolet ligthography), but the transistor design was replaced with stacks of nanosheets.

We are still waiting for 7nm FinFET chips to hit the market and that is perhaps why IBM compared the new 5nm Nanosheet chips with 10nm technology.

5nm silicon nanosheet transistors.

As Mukesh Khare, vice president of semiconductor technology research at IBM Research explains, the industry is racing to move beyond FinFET design because it doesn't scale anymore.

Scientists at IBM Research and its partner SUNY Polytechnic Institute (Colleges of Nanoscale Science and Engineering's NanoTech Complex) have been working on nanosheet semiconductors in the lab for more than 10 years. The groundbreaking research will enable finger-nail sized chips with 30 billion transistors. This time, IBM didn't go for FinFET (fin field effect) fabrication but stacked silicon nanosheets as the device structure of the transistor, known as GAA (gate-all-around) transistor.

It's a remarkable technical achievement, though a commercial version of the chip may not be possible for a while. This is made possible by using nanosheets instead of fins as the main structure of the transistors.

IBM doesn't manufacture chips anymore, but it's still very much involved in testing and developing new manufacturing techniques that will pave the way for next generation of microprocessors.

The benefits of 5nm chips are obvious no matter how you look at it. This isn't to mention all the gazillions of chips that will be needed to power self-driving cars, servers, homes, drones, in-device artificial intelligence and 5G sensors and cameras that drive the dreams of every device maker in the world-and there are a lot of them.

This quest for faster and more efficient processors has been going on for as long as the technology has been around, and was summed up by the famous Moore's Law, put forward by Intel co-founder Gordon Moore in 1965.

Though Moore's Law has slowed down in recent years and some experts even think it's dead, chip designers continue to work their magic. But as chip designers cram more transistors closer together using FinFET design, chips are confronting issues with transistor leakage. "I'd say nearly half of the major innovations have probably come from that alliance".

Nevertheless, the escalation in computing demand is making some of the economic arguments against continued transistor shrinkage irrelevant.

More details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits Conference in Kyoto, Japan.

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